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(R)
TDA7500
DIGITAL AM/FM SIGNAL PROCESSOR
PRODUCT PREVIEW
FULL SOFTWARE FLEXIBILITY WITH TWO 24X24 BIT DSP CORES AM/FM PROCESSING AUDIO-PROCESSING AND SOUND-PROCESSING HARDWARE RDS FILTER, DEMODULATOR & DECODER INTEGRATED CODEC IIC AND SPI CONTROL INTERFACES SPI DEDICATED TO DISPLAY MICRO 6 CHANNEL SERIAL AUDIO INTERFACE SAI SPDIF RECEIVER WITH SAMPLE RATE CONVERTER EXTERNAL MEMORY INTERFACE DOUBLE DEBUG INTERFACE ON-CHIP PLL 5V-TOLERANT 3V I/O INTERFACE MULTIFUNCTION GENERAL PURPOSE I/O PORTS BLOCK DIAGRAM
Mute
TQFP100 Power with Slug Down
DESCRIPTION The TDA7500 is an integrated circuit implementing a fully digital, integrated and advanced solution to perform the signal processing in front of the power amplifier and behind the AM/FM tuner or any other audio sources. The chip integrates two 43 MIPs DSP cores: one for stereo decoding, noise blanking, weak signal processing and multi-
analog audio in AM-IF CC CD tel,navi AM/FM lev. AM/FM mpx RDS mpx
1 2 3 4 2 3 1
supply Cref 2 2 AM Noise Detector
VS 3
SigGnd RefOut
Input Multiplexer, Analog Level Adjust
IIC
2 channel analog bypass CODEC-ref
Output Analog Volume Control, select. Line Driver
6
signal/line out
4 Modulator Modulator Modulator Modulator
Main micro
VDD GND 3 2 Decimation Filter Decimation Filter
DAC-ref
6
Voltage Ref. Codec Ctl Reg. Test I/F
uP control (4 I/O's) 4
IIC / SPI SPI XTAL Osc., PLL Ext. Memory Interface Serial Audio Interface SPDIF Interface Mux Grp & blk RDS sync., error Demod. Filter correction Exchange Interface
Oversampling Filter Oversampling Filter Oversampling Filter
Noise Shaper Noise Shaper Noise Shaper X bus 0
SC Filter SC Filter SC Filter SC Filter SC Filter SC Filter X Register Ram 512 Y Register Ram 512 Program Ram 5632 Rom 256
Display uP (4 I/O's) 4 Spectrum Analyser CLK in Audio Bus Synch. 8.55MHz Data, ctl 8+3 128k (4M) x 8 17 Address (1 I/O) Audio Bus 6 ch. 3 dig. aud. out (2 I/O's) 4 clkt, wst, clkr, wsr 2 dig. aud. in (2 I/O's) CD input CDC input MD input RDS bit/blk Int.(1 I/O) RDS (4 I/O's) 4
X bus 1 X Register Ram 512 Y Register Ram 512 Program Ram 1024 Rom 256 DSP Orpheus Core including 12 GPIO* s FM processing, AM processing, Traffic mem., Dolby, Speech synth., etc... Debug, Test Interface
1 stereo channel Sample Rate Converter DSP Orpheus Core including 12 GPIO* s Audio processing, Sound processing Debug, Test Interface 5 5 2 4 4 Int Reset VDD GND Test (3 I/O's) (3 I/O's)
SPI
Error corrected RDS blocks alternatively: RDS clk, dat, qual, ARI
RDS
DSP1
DSP0
September 1999
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
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TDA7500
path detection and one for sound processing. An I2C/SPI interface is implemented for control and communication with the main micro. A separate SPI is available to interface the display micro. The DSP cores are integrated with their associated data and program memories. The peripherals and interfaces I2C, SPI, Serial Audio Interface (SAI), PLL Oscillator, External Memory Interface, (EMI), General Purpose I/O register (Port A) and the D/A registers are connected to and controlled ABSOLUTE MAXIMUM RATINGS
Symbol VDD VCC Power supplies Analog Input Voltage Tamb Tstg Digital Input Voltage Operating Temperature Range Storage Temperature Parameter Digital Analog Value 4.6 4.6 -0.5 to (VDD+0.5) -0.5 to (VCC+0.5) -40 to 85 -55 to 150 Unit V V V V C C
by DSP0, whereas the A/D registers, the SPDIF and the General Purpose I/O register (Port B) are connected to and controlled by DSP1. The Debug and Test Interface are connected to both DSP cores. The TDA7500 is supposed to be used in kit with the TDA7501 or any other device of the same family. Thanks to the serial audio interface also digital sources can be processed and a direct output to a digital bus is also available.
Warning: Operation at or beyond these limit may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
PIN CONNECTION
DBRQN0 VDD2 GND2 COVDD2 COGND1 COIN<0> COIN<1> COIN<2> COIN<3> COVDD1 S2DREF VREF2 VREF1 VREF0 COUT<0> COUT<1> COUT<2> COUT<3> COUT<4> COUT<5> CGND0 CVDD0 CODEC2 CODEC1 CODEC0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 DSP0 GPIO9 DSP0 GPIO11 DSP0 GPIO10 DSP1 GPIO9 DSP1 GPIO11 DSP1 GPIO10
DSP0 GPIO0 DSP0 GPIO1 DSP0 GPIO2 DSP0 GPIO3 DSP0 GPIO4 DSP0 GPIO5 DSP0 GPIO6 DSP0 GPIO7
DSP1 GPIO4 DSP1 GPIO3 DSP1 GPIO2 DSP1 GPIO1 DSP1 GPIO0
TESTEN TESTSE NRESET SCKM MISOM MOSIM SSM SCKD MISOD MOSID SSD AVDD XTI XTO CLKIN AGND RDSINT RDSARI_SCLK RDSQAL_SO RDSDAT_SI RDSCLK_SS INT SRCCD SRCMD GND1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Test
CODEC
Debug DSP0
IIC/SPI master
Control Inputs
Debug DSP1
SPI display
SAI
PLL oscillator
RDS
EMI SPDIF + Sample Rate Converter 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DBCK0OS01 DBIN0OS00 DBOUT0 DBRQN1 DBCK1_OS11 DBIN1_OS10 DBOUT1 LRCKR SCKR LRCKT SCKT SDI0 SDI1 / SRA<21> SDI2 / SRA<20> SDO0 / SRA<19> SDO1 / SRA<18> SDO2 / SRA<17> CASALE DRD DWR SRA<16> SRA<15> SRA<14> SRA<13> CVDD2
SRCCDC DSP1 GPIO5 DSP1 GPIO6 DSP1 GPIO7 DSP1 GPIO8
DSP0 GPIO8
CGND2 SRA<12> SRA<11> SRA<10> SRA<9> SRA<8> SRA<7> SRA<6> SRA<5> SRA<4> SRA<3> SRA<2> SRA<0> SRA<1> DSRA<0> DSRA<1> DSRA<2> DSRA<3> DSRA<4> DSRA<5> DSRA<6> DSRA<7> CVDD1 CGND1 VDD1
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PIN DESCRIPTION
N 1 2 3 NAME GND1 VDD1 TESTEN TYPE DESCRIPTION Ground pin dedicated to the digital periphery. Supply pin dedicated to the digital periphery. Test Enable (Input). When active, puts the chip into test mode and muxes the XTI clock to all flip-flops. When TEST_SE is also active, the scan chain shifting is enabled. SCAN Enable (Input). When active with TESTEN also active, controls the shifting of the internal scan chains. When active with TESTEN not active, sets all tri-state outputs into hi-impedance mode System Reset (Input). A low level applied to NRESET input initializes the IC. I2C Serial Clock Line (Input/Output)/SPI Bit Clock (Input)/General Purpose I/O (Input/Output). Clock line for I2C bus. Schmitt trigger input. If SPI interface is enabled, behaves as SPI bit clock. Optionally it can be used as general purpose I/O controlled by DSP0. I2C Serial Data Line (Input/Output)/SPI Master Input Slave Output Serial Data (Input/Output)/General Purpose I/O (Input/Output). Data line for I2C bus. Schmitt trigger input. If SPI is enabled, behaves as Serial Data Input when in SPI Master Mode and Serial Data Output when in SPI Slave Mode. Optionally it can be used as general purpose I/O controlled by DSP0. SPI Master Output Slave Input Serial Data (Input/Output)/General Purpose I/O (Input/Output). Serial Data Output when in SPI Master Mode and Serial Data Input when in SPI Slave Mode. Optionally it can be used as general purpose I/O controlled by DSP0. SPI Slave Select (Input)/General Purpose I/O (Input/Output). If SPI is enabled, behaves as Slave Select line for SPI bus. Optionally it can be used as general purpose I/O controlled by DSP0. SPI Bit Clock (Input)/General Purpose I/O (Input/Output). SPI bit clock. Schmitt trigger input. Optionally it can be used as general purpose I/O controlled by DSP0. SPI Master Input Slave Output Serial Data (Input/Output)/General Purpose I/O (Input/Output). Schmitt trigger input. Behaves as Serial Data Input when in SPI Master Mode and Serial Data Output when in SPI Slave Mode. Optionally it can be used as general purpose I/O controlled by DSP0. SPI Master Output Slave Input Serial Data (Input/Output)/General Purpose I/O (Input/Output). Serial Data Output when in SPI Master Mode and Serial Data Input when in SPI Slave Mode. Optionally it can be used as general purpose I/O controlled by DSP0. SPI Slave Select (Input)/General Purpose I/O (Input/Output). Behaves as Slave Select line for SPI bus. Optionally it can be used as general purpose I/O controlled by DSP0. Clock Input pin (Input). Clock from external digital audio source to synchronize the internal PLL. audio source to synchronize the internal PLL. Crystal Oscillator Input (Input). External Clock Input or crystal Oscillator input. Crystal Oscillator Output (Output). Crystal Oscillator output drive. Ground pin dedicated to the PLL RDS bit/block interrupt (Output)/General Purpose I/O (Input/Output). Provides an interrupt to the main micro. Optionally it can be used as general purpose I/O controlled by DSP1.
I
4
TESTSE
I
5 6
NRESET SCKM/DSP0_GPIO0
I I/O
7
MISOM/DSP0_GPIO1
I/O
8
MOSIM/DSP0_GPIO2
I/O
9
SSM/DSP0_GPIO3
I
10
SCKD/DSP0_GPIO4
I
11
MISOD/DSP0_GPIO5
I/O
12
MISOD/DSP0_GPIO6
I/O
13
SSD/DSP0_GPIO7
I
14 15 16 17 18 19
CLKIN AVDD XTI XTO AGND RDSINT/DSP1_GPIO4
I
I O O
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TDA7500
PIN DESCRIPTION (continued)
N 20 NAME RDSARI_SCK/DSP1_GPIO3 TYPE DESCRIPTION O SPI Bit Clock (Input)/ARI indicator (Output)/General Purpose I/O (Input/Output). Schmitt trigger input. If SPI interface is enabled, behaves as SPI bit clock. Optionally it provides the ARI indication bit. Optionally it can be used as general purpose I/O controlled by DSP1. O SPI Slave Output Serial Data (Output)/RDS Bit Quality (Output)/General Purpose I/O (Input/Output). If SPI is enabled, behaves as Serial Data Output. Optionally it provides the RDS serial data quality information. Optionally it can be used as general purpose I/O controlled by DSP1. I SPI Slave Input Serial Data (Input)/RDS Bit Data (Output)/General Purpose I/O (Input/Output). If SPI is enabled, behaves as Serial Data Input. Optionally it provides the RDS serial data stream. Optionally it can be used as general purpose I/O controlled by DSP1. I SPI Chip Select (Input)/RDS Bit Clock (Output)/General Purpose I/O (Input/Output). If SPI is enabled, behaves as Chip Select line for SPI bus. Optionally it provides the 1187.5Hz RDS Bit Clock. Optionally it can be used as general purpose I/O controlled by DSP1. I External interrupt line (Input). When this line is asserted low, the DSP may be interrupted. Ground pin dedicated to the digital core part. Supply pin dedicated to the digital core part. I SPDIF Input 1 (Input). Stereo SPDIF input to connect a digital audio source like a CD. I SPDIF Input 2 (Input). Stereo SPDIF input to connect a digital audio source like a MD. I/O DSP SRAM Data Lines<7> (Input/Output). When in SRAM Mode this pin act as the EMI data line 7. I/O DSP SRAM Data Lines<6> (Input/Output). When in SRAM Mode this pin act as the EMI data line 6. I/O DSP SRAM Data Lines<5> (Input/Output). When in SRAM Mode this pin act as the EMI data line 5. I/O DSP SRAM Data Lines<4> (Input/Output). When in SRAM Mode this pin act as the EMI data line 4. I/O DSP SRAM Data Line<3> (Input/Output)/DSP DRAM Data Line<3> (Input/Output). This pin act as the EMI data line 3 in both SRAM Mode and DRAM Mode. I/O DSP SRAM Data Line<2> (Input/Output)/DSP DRAM Data Line<2> (Input/Output). This pin act as the EMI data line 2 in both SRAM Mode and DRAM Mode. I/O DSP SRAM Data Line<1> (Input/Output)/DSP DRAM Data Line<1> (Input/Output). This pin act as the EMI data line 1 in both SRAM Mode and DRAM Mode. I/O DSP SRAM Data Line<0> (Input/Output)/DSP DRAM Data Line<0> (Input/Output). This pin act as the EMI data line 0 in both SRAM Mode and DRAM Mode. O DSP SRAM Address Line<0> (Output)/DSP DRAM Address Line<0> (Output). This pin act as the EMI address line 0 in both SRAM Mode and DRAM Mode. O DSP SRAM Address Line<1> (Output)/DSP DRAM Address Line<1> (Output). This pin act as the EMI address line 1 in both SRAM Mode and DRAM Mode.
21
RDSQAL_SO/DSP1_GPIO2
22
RDSDAT_SI/DSP1_GPIO1
23
RDSCLK_SS/DSP1_GPIO0
24 25 26 27 28 29 30 31 32 33
INT CGND1 CVDD1 SCRCCD SCRCMD DSRA<7> DSRA<6> DSRA<5> DSRA<4> DSRA<3>
34
DSRA<2>
35
DSRA<1>
36
DSRA<0>
37
SRA<0>
38
SRA<1>
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TDA7500
PIN DESCRIPTION (continued)
N 39 NAME SRA<2> TYPE DESCRIPTION O DSP SRAM Address Line<2> (Output)/DSP DRAM Address Line<2> (Output). This pin act as the EMI address line 2 in both SRAM Mode and DRAM Mode. O DSP SRAM Address Line<3> (Output)/DSP DRAM Address Line<3> (Output). This pin act as the EMI address line 3 in both SRAM Mode and DRAM Mode. O DSP SRAM Address Line<4> (Output)/DSP DRAM Address Line<4> (Output). This pin act as the EMI address line 4 in both SRAM Mode and DRAM Mode. O DSP SRAM Address Line<5> (Output)/DSP DRAM Address Line<5> (Output). This pin act as the EMI address line 5 in both SRAM Mode and DRAM Mode. O DSP SRAM Address Line<6> (Output)/DSP DRAM Address Line<6> (Output). This pin act as the EMI address line 6 in both SRAM Mode and DRAM Mode. O DSP SRAM Address Line<7> (Output)/DSP DRAM Address Line<7> (Output). This pin act as the EMI address line 7 in both SRAM Mode and DRAM Mode. O DSP SRAM Address Line<8> (Output)/DSP DRAM Address Line<8> (Output). This pin act as the EMI address line 8 in both SRAM Mode and DRAM Mode. O DSP SRAM Address Line<9> (Output)/DSP DRAM Address Line<9> (Output). This pin act as the EMI address line 9 in both SRAM Mode and DRAM Mode. O DSP SRAM Address Line<10> (Output)/DSP DRAM Address Line<10> (Output). This pin act as the EMI address line 10 in both SRAM Mode and DRAM Mode. O DSP SRAM Address Line<11> (Output)/DSP DRAM Address Line<11> (Output). This pin act as the EMI address line 11 in both SRAM Mode and DRAM Mode. O DSP SRAM Address Line<12> (Output)/DSP DRAM Address Line<12> (Output). This pin act as the EMI address line 12 in both SRAM Mode and DRAM Mode. Ground pin dedicated to the digital core part. Supply pin dedicated to the digital core part. O DSP SRAM Address Line<13> (Output)/DSP DRAM Address Line<13> (Output). This pin act as the EMI address line 13in both SRAM Mode and DRAM Mode. O DSP SRAM Address Line<14> (Output)/DSP DRAM Address Line<14> (Output). This pin act as the EMI address line 14 in both SRAM Mode and DRAM Mode. O DSP SRAM Address Line<15> (Output)/DSP DRAM Address Line<15> (Output). This pin act as the EMI address line 15 in both SRAM Mode and DRAM Mode. O DSP SRAM Address Line<16> (Output)/DSP DRAM Address Line<16> (Output)/General Purpose I/O (Input/Output). This pin acts as the EMI address line 16 in both SRAM Mode and DRAM Mode. Optionally it can be used as general purpose I/O controlled by DSP0. O DSP SRAM Write Enable (Output)/DRAM Write Enable (Output). This pin serves as the write enable for the EMI in both DRAM and SRAM Mode. O DSP SRAM Read Enable(Output)/DRAM Read Enable (Output). This pin serves as the read enable for the EMI in both DRAM and SRAM Mode.
40
SRA<3>
41
SRA<4>
42
SRA<5>
43
SRA<6>
44
SRA<7>
45
SRA<8>
46
SRA<9>
47
SRA<10>
48
SRA<11>
49
SRA<12>
50 51 52
CGND2 CVDD2 SRA<13>
53
SRA<14>
54
SRA<15>
55
SRA<16>/DSP0_GPIO8
56
DWR
57
DRD
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TDA7500
PIN DESCRIPTION (continued)
N 58 59 NAME CASALE SDO<2>/SRA<17>/DSP1_GPIO<8 > TYPE DESCRIPTION O DSP DRAM Column Address Strobe (Output). When in DRAM Mode this pin acts as the column address strobe. O SAI Outputs (Output)/EMI SRAM Address Line<17> (Output)/General Purpose I/O (Input/Output). One stereo channel SAI data output in SAI mode. EMI address line 17 in SRAM Mode. Optionally it can be used as a general purpose I/O. O SAI Outputs (Output)/EMI SRAM Address Line<18> (Output)/General Purpose I/O (Input/Output). One stereo channel SAI data output in SAI mode. EMI address line 18 in SRAM Mode. Optionally it can be used as a general purpose I/O. O SAI Output (Output)/EMI SRAM Address Line<19> (Output). One stereo channel SAI data output in SAI mode. EMI address line 19 in SRAM Mode. I SAI Input (Input)/EMI SRAM Address Line<20> (Output)/General Purpose I/O (Input/Output). One stereo channel SAI data input in SAI mode. EMI address line 20 in SRAM Mode. Optionally it can be used as a general purpose I/O. I SAI Input (Input)/EMI SRAM Address Line<21> (Output)/DRAM Row Address Strobe (Output)/General Purpose I/O (Input/Output). One stereo channel SAI data input in SAI mode. EMI address line 21 in SRAM Mode. When in DRAM Mode this pin acts as the row address strobe. Optionally it can be used as a general purpose I/O. I SAI Input (Input)/SPDIF Input 3 (Input). One stereo channel SAI data input in SAI mode. Stereo SPDIF input intended to connect a digital audio source like a CD changer in SPDIF mode. I/O SAI transmitter Bit Clock (Input/Output). SAI transmitter bit clock. Master or slave. I/O SAI transmitter Left-Right Clock (Input/Output). SAI transmitter Left-Right clock. Can be master or slave mode. I/O SAI receiver Bit Clock (Input/Output). SAI receiver bit clock. I/O SAI receiver Left-Right Clock (Input/Output). SAI receiver LeftRight clock. I/O Debug Port Serial Output (Input/Output)/ General Purpose I/O (Input/Output). The serial data output for the Debug Port. Optionally it can be used as a general purpose I/O. I/O Debug Port Serial Input/Chip Status 0 (Input/Output)/ General Purpose I/O (Input/Output). The serial data input for the Debug Port is provided when an input. When an output, together with OS1 provides information about the chip status. Optionally it can be used as a general purpose I/O. I/O Debug Port Bit Clock/Chip Status 1 (Input/Output)/General Purpose I/O (Input/Output). The serial clock for the Debug Port is provided when an input. When an output, together with OS0 provides information about the chip status. Optionally it can be used as a general purpose I/O. I Debug Port Request Input (Input). Means of entering the Debug mode of operation. I/O Debug Port Serial Output (Input/Output)/ General Purpose I/O (Input/Output). The serial data output for the Debug Port. Optionally it can be used as a general purpose I/O. I/O Debug Port Serial Input/Chip Status 0 (Input/Output)/ General Purpose I/O (Input/Output). The serial data input for the Debug Port is provided when an input. When an output, together with OS1 provides information about the chip status. Optionally it can be used as a general purpose I/O.
60
SDO<2>/SRA<18>/DSP1_GPIO<7 >
61
SDO<0>/SRA<19>
62
SDI<2>/SRA<20>/DSP1_GPIO<6>
63
SDI<1>/SRA<21>/RAS/DSP1_GPIO<5>
64
SDI<0>/SRCCDC
65 66 67 68 69
SCKT LRCKT SCKR LRCKR DBOUT1/DSP1_GPIO10
70
DBIN1/OS10/DSP1_GPIO11
71
DBCK1/OS11/DSP1_GPIO9
72 73
DBRQN1 DBOUT0/DSP0_GPIO10
74
DBIN0/OS00/DSP0_GPIO11
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PIN DESCRIPTION (continued)
N 75 NAME DBCK0/OS01/DSP0_GPIO9 TYPE DESCRIPTION I/O Debug Port Bit Clock/Chip Status 1 (Input/Output)/General Purpose I/O (Input/Output). The serial clock for the Debug Port is provided when an input. When an output, together with OS0 provides information about the chip status. Optionally it can be used as a general purpose I/O. I Debug Port Request Input (Input). Means of entering the Debug mode of operation. Supply pin dedicated to the digital periphery. Ground pin dedicated to the digital periphery. I Analog Inputs (Input). Single ended analog signal inputs to the ADC. I Analog Inputs (Input). Single ended analog signal inputs to the ADC. I Analog Inputs (Input). Single ended analog signal inputs to the ADC. I Analog Inputs (Input). Single ended analog signal inputs to the ADC. I Voltage Reference (Input). External decoupling of the analog reference used for the single to differential ended converter. I Voltage Reference (Input). Analog voltage reference input. Signal is supplied by A354. I Voltage Reference (Input). External decoupling of the analog references used for the sigma delta modulator. I Voltage Reference (Input). External decoupling of the analog references used for the sigma delta modulator. I Voltage Reference (Input). External decoupling of the analog references used for the sigma delta modulator. Analog Supply pin dedicated to the A/D converter. Analog Ground pin dedicated to the A/D converter. O Analog Outputs (Output). Analog signal outputs of the DAC O Analog Outputs (Output). Analog signal outputs of the DAC O Analog Outputs (Output). Analog signal outputs of the DAC O Analog Outputs (Output). Analog signal outputs of the DAC O Analog Outputs (Output). Analog signal outputs of the DAC O Analog Outputs (Output). Analog signal outputs of the DAC I Voltage Reference (Input). External decoupling of the analog references of the CODEC. I Voltage Reference (Input). External decoupling of the analog references of the CODEC. I Voltage Reference (Input). External decoupling of the analog references of the CODEC. Analog Ground pin dedicated to the D/A converter. Analog Supply pin dedicated to the D/A converter.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
DBRQN0 VDD2 GND2 ADC<0> ADC<1> ADC<2> ADC<3> S2DREF ADCVDDREF ADCREF<2> ADCREF<1> ADCREF<0> ADCVDD ADCGND DAC<0> DAC<1> DAC<2> DAC<3> DAC<4> DAC<5> DACREF<2> DACREF<1> DACREF<0> DACGND DACVDD
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TDA7500
RECOMMENDED DC OPERATING CONDITIONS
Symbol VDDC Tj Parameter 3.3V Power Supply Voltage Operating Junction Temperature Test Condition Min. 3 -40 Typ. 3.3 Max. 3.6 125 Unit V C
POWER CONSUMPTION
Symbol Idd Parameter Maximum current for core power supply @3.3V Value 450 Unit mA
Note: 43MHz internal DSP clock at Tamb
ADC PERFORMANCE Some of the relevant ADC parameters are reported in the following table: (T = 25C, AVDD = 3.3V, measurement bandwidth 10Hz to 20KHz, A-Weighted Filter.)
Symbol Parameter Maximum input level (1) Sample rate Frequency Response Instant Dynamic Range SNR (THD + N)/S PSRR Input Impedance Crosstalk Gain mismatch between four input CMRR CM Input range
(1) Corresponding to 2VRMS Maximum Differential Input.
Test Condition
Min. 32
Typ.
Max. 1 48
Unit Vrms KHz dB dB dB dB dB K dB
@ 20KHz with fs = 44.1KHz -60dB analog input 1KHz; -3dB analog input -3dB analog input 0.1Vp @ 1KHz 1Vrms input @ 15KHz @ 1KHz @ 1KHz 90 90 45 10 70 -0.5 40
-3 93 93 -85 30 0.5
dB dB mV
100
DAC PERFORMANCE Some of the relevant DAC parameters are reported in the following table: (T = 25C, AVDD = 3.3V, measurement bandwidth 10Hz to 20KHz, A-Weighted Filter 0dB gain, output load 30k)
Symbol Parameter Maximum output level (1) Sample rate Frequency Response Dynamic Range SNR Total D R Digital Silence (THD + N)/S PSRR Output Impedance Crosstalk Gain mismatch between six outputs Test Condition Min. 32 @ 20KHz with fs = 44.1KHz -60dB analog input 1KHz -3dB analog output 0000$ digital input -3dB analog input 0.1Vp @ 1KHz 1Vrms output @ 15KHz @ 1KHz 90 90 -3 93 93 100 93 -85 45 30 70 -0.5 Typ. Max. 1 48 Unit Vrms KHz dB dB dB dB dB dB dB k dB dB
0.5
(1) Corresponding to 2VRMS Maximum Differential Output.
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FUNCTIONAL DESCRIPTION. The TDA7500 IC broken up into two distinct blocks. One block contains the two DSP Cores and their associated peripherals. The other contains the ADC, DAC and the RDS filter, demodulator and decoder. 24-BIT DSP CORE. The two DSP cores are used to process the audio and FM/AM data, coming from the ADC, either any kind of digital data coming via SPDIF or SAI. After the digital signal processing these data are sent to the DAC for analog conversion. Functions such as volume, tone, balance, and fader control, as well as spatial enhancement and general purpose signal processing may be performed by the DSP0. When FM/AM mode is selected, DSP1 is fully devoted to AM/FM processing. Nevertheless it can be used for any kind of different application, when a different input source is selected. Some capabilities of the DSPs are listed below: Single cycle multiply and accumulate with convergent rounding and condition code generation 2 x 56-bit Accumulators Double precision multiply Scaling and saturation arithmetic 48-bit or 2 x 24-bit parallel moves 64 interrupt vector locations Fast or long interrupts possible Programmable interrupt priorities and masking 8 each of Address Registers, Address Offset Registers and Address Modulo Registers Linear, Reverse Carry, Multiple Buffer Modulo, Multiple Wrap-around Modulo address arithmetic Post-increment or decrement by 1 or by offset, Index by offset, predecrement address Repeat instruction and zero overhead DO loops Hardware stack capable of nesting combinations of 7 DO loops or 15 interrupts/subroutines Bit manipulation instructions possible on all registers and memory locations. Also Jump on bit test. 4 pin serial debug interface Debug ccess to all internal registers, buses and memory locations 5 word deep program address history FIFO Hardware and software breakpoints for both program and data memory accesses Debug Single stepping, Instruction injection and Disassembly of program memory
DSP PERIPHERALS There are a number of peripherals that are tightly coupled to the two DSP Cores. Same of the peripherals are connected to DSP 0 others are connected to DSP1. 512 x 24-Bit X-RAM. 512 x 24-Bit Y-RAM. 1024 x 24-Bit Program RAM (5.5K x 24 for DSP1) 128 x 24-Bit Boot ROM for each DSP. Serial Audio Interface (SAI) SPDIF receiver with sampling rate conversion I2C and SPI interface XCHG Interface for DSP to DSP communication. External Memory Interface (DRAM/SRAM) for time-delay and traffic information. Double Debug Port DATA AND PROGRAM MEMORY Both DSP0 and DSP1 have an identical set of Data and Program memories attached to them. Each of the memories are described below and it is implied that there are two of each type, one set connected to DSP0 and the other to DSP1. The only exception is the case of the P-RAM where DSP0 has a 1024 x 24-Bit PRAM and DSP1 has a 5.5K x 24-Bit PRAM. 512 x 24-Bit X-RAM (XRAM) This is a 512 x 24-Bit Single Port SRAM used for storing coefficients. The 16-Bit XRAM address, XABx(15:0) is generated by the Address Generation Unit of the DSP core. The 24-Bit XRAM Data, XDBx(23:0), may be written to and read from the Data ALU of the DSP core. The XDBx Bus is also connected to the Internal Bus Switch so that it can be routed to and from all peripheral blocks. 512 x 24 Bit Y-RAM (YRAM) This is a 512 x 24-Bit Single Port SRAM used for storing coefficients. The 16-Bit address, YABx(15:0) is generated by the Address Generation Unit of the DSP core. The 24-Bit Data, YDBx(23:0), is written to and read from the Data ALU of the DSP core. The YDBx Bus is also connected to the Internal Bus Switch so that it can be routed to and from other blocks. 1024 x 24-Bit Program RAM (PRAM 5.5K x 24-bit for DSP1) This is a 1024 x 24-Bit Single Port SRAM used for storing and executing program code. The 169/14
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Bit PRAM Address, PABx(15:0) is generated by the Program Address Generator of the DSP core for Instruction Fetching, and by the AGU in the case of the Move Program Memory (MOVEM) Instruction. The 24-Bit PRAM Data (Program Code), PDBx(23:0), can only be written to using the MOVEM instruction. During instruction fetching the PDBx Bus is routed to the Program Decode Controller of the DSP core for instruction decoding. 256 x 24-Bit Bootstrap ROM (PROM) This is a 256 x 24-Bit factory programmed Boot ROM used for storing the program sequence and for initializing the DSP. Essentially this consists of reading the data via I2C, SPI or EMI interface and store it in PRAM, XRAM, YRAM, and/or external DRAM. Serial Audio Interface (SAI) The SAI is used to deliver digital audio to the DSPs from an external source. Once processed by the DSPs, it can be returned through this interface either sent to the DAC for D/A conversion. The features of the SAI are listed below. 3 Synchronized Stereo Data Transmission Lines 3 Synchronized Stereo Data Reception Lines Master and Slave operating mode: clock lines can be both master and slave. Receive and Transmit Data Registers have two locations to hold left and right data. XCHG Interface (DSP to DSP Exchange Interface) The Exchange Interface peripheral provides bidirectional communication between DSP0 and DSP1. Both 24 bit word data and four bit Flag data can be exchanged. A FIFO is utilized for received data. It minimizes the number of times an Exchange Interrupt Service Routine would have to be called if multi-word blocks of data were to be received. The Transmit FIFO is in effect the Receive FIFO of the other DSP and is written directly by the transmitting DSP. The features of the XCHG are listed below. 10 Word XCHG Receive FIFO on both DSPs Four Flags for each XCHG for DSP to DSP signaling Condition flags can optionally trigger interrupts on both DSPs DRAM/SRAM Interface (EMI) The External DRAM/SRAM Interface is viewed as a memory mapped peripheral. Data transfers are performed by moving data into/from data registers and the control is exercised by polling status
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flags in the control/status register or by servicing interrupts. An external memory write is executed by writing data into the EMI Data Write Register. An external memory read operation is executed by either writing to the offset register or reading the EMI Data Read Register, depending on the configuration. The features of the EMI are listed below. Data bus width fixed at 4 bits for DRAM and 8 bits for SRAM. Data word length 16 or 24 bits for DRAM. Data word length 8or 16 or 24 bits for SRAM. Thirteen DRAM address lines means 226 = 32MB addressable DRAM. Refresh rate for DRAM can be chosen among eight divider factor. SRAM relative addressing mode; 222 = 4MB addressable SRAM. Four SRAM Timing choices. Two Read Offset Registers. Debug Interface A dedicated Debug Port is available for each DSP Cores. The debug logic is contained in the core design of the DSP. The features of the Debug Port are listed below: Breakpoint Logic Trace Logic Single stepping Instruction Injection Program Disassembly Serial Peripheral Interface The DSP core requires a serial interface to receive commands and data over the LAN. During an SPI transfer, data is transmitted and received simultaneously. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slave SPI device. When an SPI transfer occurs an 8-bit word is shifted out one data pin while another 8-bit character is simultaneously shifted in a second data pin. The central element in the SPI system is the shift register and the read data buffer. The system is single buffered in the transfer direction and double buffered in the receive direction. I2C Interface The inter Integrated Circuit bus is a single bidirectional two-wire bus used for efficient inter IC control. All I2C bus compatible devices incorporate an on-chip interface which allows them communicate directly with each other via the I2C bus.
TDA7500
Every component hooked up to the I2C bus has its own unique address whether it is a CPU, memory or some other complex function chip. Each of these chips can act as a receiver and /or transmitter on its functionality. General Purpose Input/Output The DSP requires a set of external general purpose input/output lines, and a reset line. These signals are used by external devices to signal events to the DSP. The GPIO lines are implemented as DSP 's peripherals. The GPIO lines are grouped in Port A which is connected to DSP 0, and Port B, which is connected to DSP1. PLL Clock Oscillator The PLL Clock Oscillator can accept an external clock at XTI or it can be configured to run an internal oscillator when a crystal is connected across pins XTI & XTO. There is an input divide block IDF (1 -> 32) at the XTI clock input and a multiply block MF (9 -> 128) in the PLL loop. Hence the PLL can multiply the external input clock by a ratio MF/IDF to generate the internal clock. This allows the internal clock to be within 1 MHz of any desired frequency even when XTI is much greater than 1 MHz. It is recommended that the input clock is not divided down to less than 1 MHz as this reduces the Phase Detector's update rate. The clocks to the DSP can be selected to be either the VCO output divided by 2 to 16, or be driven by the XTI pin directly. The crystal oscillator and the PLL will be gated off when entering the power-down mode (by setting a register on DSP0). Codec The CODEC is composed of four AD mono converters, three DA stereo converters. The ADC can operate both in audio mode and in FM/AM mode. When in audio mode, it converts the audio bandwidth from 20 to 20KHz. The A to D is a third order Sigma-Delta converter, the converter resolutions is 20 bit with 93 dB of dynamic range and 85dB of total harmonic distortion. When in FM mode, the converted bandwidth is up to 192KHz. The D to A is a third order Sigma-Delta converter with a low noise reconstructing analog filter, the converter resolution is 20 bit with 93 dB of dynamic range and 85dB of total harmonic distortion. All the reference voltages are generated inside the chip. Some capabilities of the CODEC are listed below: 20-Bit Resolution Digital Anti-Alias Filtering embedded Adjustable System Sampling Rates 93dB D/A Dynamic Range (A-Weighted) 93dB A/D Dynamic Range (A-Weighted) 85dB D/A (THD+N/S) 85dB A/D (THD+N/S) Internal Differential Analog Architecture +3.3V Power Supply SOFTWARE FEATURES A great flexibility is guaranteed by the two programmable DSP cores. A list of the main software functions which can be implemented in the TDA7500 is enclosed hereafter. A block diagram of the audio processing flow is shown in Fig. 1 below. AM/FM Baseband Signal Processing FM weak signal processing Integrated 19 kHz MPX filter and deemphasis flexible noise cancellation flexible multipath detector Generic Audio Signal Processsing Loudness Bass, treble, fader control Volume control Distortion Limiting Premium Equalization Soft mute TAPE Signal Processsing Dolby B Noise Reduction Automatic Music Search CD Signal Proceessing Dynamic Range Compression Audiophile (optional) Parametric Equalization Crossover Patters Channel Delays Center Channel Imaging Output Audio Noise Reduction Application Scheme The TDA7500 can operate as a standalone device either it can interface the TDA7501 which contains the analog input multiplexer, analog volume control and the line-driver. The FM_MPX and FM_LEVEL signals coming from the tuner and other signals supplied by analog sources are adapted by the TDA7501 and fed to the TDA7500. A block diagram of the system is shown in Fig.2 below. The TDA7500 converts all the analog signals into
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digital domain and performs AM/FM processing and audio/sound processing. Thanks to this, it is possible to process any audio source as well analog as digital in parallel, to record FM mono for traffic information, telephone response, navigation and RDS. Finally the digital signals are D/A converted and sent to the TDA7501 for the final level adjustment and for the analog volume control.
Figure 1. Software Block Diagram of Audio & Sound Processing
DLY ANR Stereo input DRC LD B T PEQ SM HP RM DLY DLY DLY DLY Dynamic Loudness Bass Audio noise range reduction compression Treble Parametric Soft mute equaliser LP Routing Delay matrix
RF CF LF RR LR SW
+
ANR
DRC
LD
B
T
PEQ
SM
HP
Figure 2. Block Diagram of Car Amplifier Audio Sub-System.
ANALOG INPUT
FRONT END TDA7421
I2C/SPI
TDA7501
AUDIO POWER
MAIN MICRO
A/D
D/A
DISPLAY MICRO
TDA7500
DIGITAL OUT
SPDIF EEPROM/ FLASH DIGITAL IN DRAM/ SRAM
D98AU946A
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TDA7500
mm DIM. A A1 A2 B C D D1 D3 e E E1 E3 H L L1 S S1 K ccc 8.80 8.80 0.45 0.05 1.35 0.17 0.09 16.00 14.00 12.00 0.50 16.00 14.00 12.00 9.85 0.60 1.00 0.346 0.346 0 (min.), 3.5 (typ.), 7(max.) 0.080 0.003 0.75 0.018 1.40 0.22 MIN. TYP. MAX. 1.60 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.003 0.630 0.551 0.472 0.020 0.630 0.551 0.472 0.388 0.024 0.039 0.030 0.055 0.009 MIN. inch TYP. MAX. 0.063 0.006 0.057 0.011 0.008
OUTLINE AND MECHANICAL DATA
TQFP100 (14x14x1.40mm) with Slug Down (10x10mm)
D D1 D3
SEATING PLANE C
A A2
A1
75 76 51 50
ccc C
e H S1 E3 E1 E
B
0.25mm
PIN 1 IDENTIFICATION
100 1 25 26
.010 inch GAGE PLANE
C K
TQFP100M
S
L L1
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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